This invention concerns a phase discriminator that detects the difference in phase between a pair of clock signals and produces an output for changing the frequency of one of the clock signals to a frequency that reduces the measured phase difference.
Existing phase discriminators employed to detect the difference in phase between a pair of clock signals typically employ circuitry that is sensitive to race conditions when the clock edges used to mark phase arrive at substantially the same time. Stated differently, in such circuits, the closer in phase the clocks become, the less stable are the circuits.
A typical discriminator used to measure the phase difference between a pair of clock signals, C.sub.1 and C.sub.2, is illustrated in FIG. 1 and includes a pair of latches, L.sub.1 and L.sub.2. Each latch is set by a respective one of the gates G.sub.1 and G.sub.2. Each gate receives one of the clock signals (through a pulse shaper PS) and the output of the other latch. Either latch is set when the output of its gate is changed by a change in state of the associated input clock. The leading clock will set its associated latch first, causing an error signal E to be produced that indicates the time by which that clock leads the other. The set latch will remain set until reset by the lagging clock. However, if a change in state of the lagging clock is presented to its gate before the lead clock latch is set, the output of the circuit will be indeterminate and can incorrectly reflect the relative phase between the signals.
As the speeds of data transfer and data processing equipments increase with each new generation of computers, the destabilizing effects of race conditions will only grow in magnitude. Therefore, there is a manifest and urgent need to reduce, and ultimately eliminate, race conditions in phase detection circuitry.